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ÇöÀç Á¢¼ÓÁßÀÎ µî·Ï »ç¿ëÀÚ´Â 0¸í, ÀÍ¸í »ç¿ëÀÚ´Â 4¸í ÀÔ´Ï´Ù. Àüü µî·Ï »ç¿ëÀÚ: 751¸í
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ÀÓº£µðµå! - FPGA Clock domain ¹®Á¦ |
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±Û¾´ÀÌ: EzDoum ±Û¾´³¯: 2005³â 08¿ù 26ÀÏ ¿ÀÈÄ 03:39 |
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FPGA¿¡¼ Ŭ·° µµ¸ÞÀÎÀÌ ¿©·¯°³¶ó ¾î·Á¿òÀ» °Ý°í ÀÖ´Ù. Ŭ·° ¼Â¾÷, Ȧµå ŸÀֿ̹¡¼ ¹®Á¦°¡ ¹ß»ýÇÏ´Â°Ç ¾î¼¸é ´ç¿¬ÇÏ´Ù. (108mhz µ¿ÀÛÇÏ´Â »óŸӽſ¡¼ ÂüÁ¶ÇÏ´Â ·¹Áö½ºÅͰ¡ 33.75mhz Ŭ·° µµ¸ÞÀÎÀÇ °Í)
°¢Á¾ ¹®¼µé¿¡¼ ¸»ÇÏ´Â °Í ó·³ synchronous ÇÏ°Ô ¼³°è°¡ µÇ¸é ÁÁ°ÚÁö¸¸ ÇØ°áÇØ¾ß ÇÏ´Â ¹®Á¦°¡ asynchronous À롃 ¾îÂîÇ϶õ ¸»Àΰ¡. °á±¹ ºñµ¿±â ¹æ½ÄÀ» µ¿±â·Î Àâ¾ÆÁÖ´Â ·ÎÁ÷ÀÌ ÇÊ¿äÇÏ´Â °Çµ¥, »ý°¢ ¸¸Å ¾ÈµÈ´Ù.
ÀÌ·²¶© ÇÏ´ø°É ¸ØÃß°í ±âÃʺÎÅÍ ´Ù½Ã ºÁÁÙ Çʿ䰡 ÀÖ´Ù. »çÀÌŬ·ÐÀ̶û ÄõÅͽº ÇÚµåºÏ ±×¸®°í ÀÎÅͳݿ¡¼ ¹®¼ Çϳª.
http://www.us.design-reuse.com/news/?id=4854&print=yes
FPGA Clock Schemes
By Tim Behne, Embedded Systems Programming
March 13, 2003 (8:30 p.m. EST)
One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.
Cyclone Device Handbook
http://www.altera.com/literature/lit-cyc.jsp
Quartus II Development Software Handbook v5.0
http://www.altera.com/literature/lit-qts.jsp
¾ÆÀ̵ð¾î
1) ³»ºÎ µà¾ó Æ÷Æ®·¥À» »ç¿ëÇØ read/write Ŭ·°ÀÌ ´Ù¸¥°ÍÀ» ÀÚ¿¬½º·´°Ô ÇØ°áÇÑ´Ù.
2) asynchronous FIFO
3) req,ack ¸¦ »ç¿ëÇÑ´Ù.
4) ¿À¹ö »ùÇøµ ??
SDRAM À» ´Ù¾çÇÏ°Ô Å×½ºÆ® ÇØºÁ¾ß°Ú´Ù.
µà¾óÆ÷Æ®·¥À¸·Î ¶óÀιöÆÛ¸¦ ¸¸µé¾ú´Âµ¥, FIFO·Îµµ ÇØº¼¸¸ ÇϰڴÙ.
[ºÐ·ù: Çϵå¿þ¾î ] |
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